Multiprocessor Scheduling to Reduce Leakage Power

In contemporary and future embedded as well as high-performance microprocessors, power consumption is one of the most important design considerations. Because in current technologies the dynamic power consumption dominates the static power consumption, voltage scaling is an effective technique to reduce the power consumption. The most common way to reduce the power consumption of multi-processor systems, is to schedule a program to run on as many processors as possible and apply voltage scaling afterwards. As technology scales to increasingly smaller feature sizes, however, the static power consumption is expected to grow exponentially. In this paper, we first show for which combinations of leakage current, supply voltage, and clock frequency the static power consumption dominates the dynamic power dissipation. Based on these results, it is at a certain point no longer advantageous to use as many processors as possible. We then present a heuristic to schedule task graphs on a number of processors that is sufficient to meet the deadline, but at the same time minimizes the power consumption. Experimental results have been obtained using our in-house power analysis tool with task graphs from real applications as well as randomly generated ones. The results show that our scheduling algorithm reduces the total energy consumption by up to 65%, compared to the strategy that schedules the tasks on the maximum number of processors and then exploits the remaining slack to lower the supply voltage.